Shift register and liquid crystal display device using the same

ABSTRACT

A shift register having a plurality of stages in which each of the stages includes: an input circuit part arranged to receive an input signal; an exclusive OR circuit arranged to generate a toggle signal by an exclusive OR operation on a non-inversion output and an inversion output of the input circuit part; and an output circuit part arranged to supply one of a clock signal and a feedback signal from an output terminal to the output terminal and an input terminal of the next stage in response to the toggle signal.

This application claims the benefit of Korean Patent Application No.P2005-0057952, filed on Jun. 30, 2005, which is hereby incorporated byreferenced for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device andmore particularly to a shift register with low capacitance loading withoverlapping outputs and a liquid crystal display device using the same.

1. Discussion of the Related Art

A liquid crystal display device controls the light transmittance ofliquid crystal cells in accordance with a video signal to display apicture.

In an active matrix type liquid crystal display device, active switchingdevices are used to control the electric fields in each liquid crystalcell to control the light transmittance of the cell. By controlling theactive switching devices, moving images can be displayed. Thin filmtransistors (hereinafter, referred to as ‘TFTs’) are primarily used asthe switching devices in an active matrix type liquid crystal displaydevice.

A liquid crystal display device of the related art, as shown in FIG. 1,includes a liquid crystal display panel 2 having a plurality of datalines 5 crossing a plurality of gate lines 6 with TFTs for drivingliquid crystal cells formed at the crossings of the gate and data lines;a data driver 3 for supplying data to the data lines 5; a gate driver 4for supplying a scan pulse to the gate lines 6; and a timing controller1 for controlling the data driver 3 and the gate driver 4.

The liquid crystal display panel 2 includes liquid crystal injectedbetween two glass substrates. The data lines 5, gate lines 6 and TFTsare formed on a lower of the two glass substrates. The TFTs supply thedata from the data lines 5 to the liquid crystal cell in response to thescan pulse from the gate lines 6. To this end, a gate electrode of theTFT is connected to the gate line 6, a source electrode is connected tothe data line 5, and, a drain electrode of the TFT is connected to apixel electrode of the liquid crystal cell Clc. Further, a storagecapacitor Cst for maintaining the voltage of the liquid crystal cell isformed on the lower glass substrate of the liquid crystal display panel

The data driver 3 includes a plurality of data integrated circuitshereinafter, referred to as ‘ICs’), and each of the data ICs includes ashift register; a register for temporarily storing stretched digitalvideo data RGB from the timing controller 1; a latch for storing thedata line by line and outputting the stored data of one line at the sametime in response to a clock signal from the shift register; adigital/analog converter for selecting a positive/negative analog gammacompensation voltage in correspondence to a digital data value from thelatch; a multiplexer for selecting the data line 5 to which thepositive/negative gamma compensation voltage is supplied; and an outputbuffer connected between the multiplexer and the data line. The datadriver 3 supplies the digital video data RGB from the timing controller1 to the data lines 5 of the liquid crystal display panel 7.

The gate driver 4 includes a shift register for sequentially generatinga scan pulse in response to a gate control signal GDC from the timingcontroller 1; a level shifter for shifting a swing width of the scanpulse to a level suitable for driving the liquid crystal cell Clc; andan output buffer. The gate driver 4 supplies the scan pulse to the gateline 6 to turn on the TFTs connected to the gate line 6, therebyselecting the liquid crystal cells Clc of a horizontal line to which apixel voltage of the data, i.e., analog gamma compensation voltage, isto be supplied. The data generated from the data driver 3 are suppliedto the liquid crystal cell Clc of the horizontal line selected by thescan pulse.

The timing controller 1 receives a digital video data RGB, a horizontalsynchronization signal H, a vertical synchronization signal H, and aclock signal CLK to generate a gate control signal GDC for controllingthe gate driver 4 and a data control signal DDC for controlling the datadriver 3. Further, the timing controller 1 supplies the data RGB to thedata driver 3.

On the other hand, in order to reduce the number of integrated circuitsof the data driver, as shown in FIG. 2, there has been proposed a liquidcrystal display device having common bus lines 201 to 240 connected toan output terminal of the data register 21 in a one-to-one relationship,and a channel selecting part 24 and a sampling & holding part 23disposed between the common bus lines 201 to 240 and the data lines DL1to DL42. A plurality of data output bus lines are formed in each of thecommon bus lines 201 to 240. For example, the first and 41^(st) dataoutput bus lines 301, 341 are connected to the first common bus line201. The channel selecting part 24 includes a plurality of switchdevices 24A that are connected to the data output bus lines 301 in theone-to-one relationship. The switch devices 24A for the channelselecting part 24 may be realized using CMOS structures and aresequentially turned on in response to the control signal from the shiftregister 22, thereby acting to supply the data from the data output buslines 301 to the sampling & holding part 23. The sampling & holding part23 sequentially samples and holds the data from the channel selectingpart 24, and then simultaneously supplies the held data to the datalines DL1 to DL42.

A shift register for making the switch devices 24A of the channelselecting part 24 sequentially operated may be realized as shown in FIG.3 or FIG. 5.

FIG. 3 illustrates a stage configuration for a shift register 22allowing overlapped output pulses. FIG. 4 illustrates input/outputwaveforms of the shift register 22 shown in FIG. 3.

Referring to FIG. 3 and 4, an arbitrary stage of the shift register 22includes a first inverter type tri-state buffer 31, a first latch 37, asecond inverter type tri-state buffer 34 and a second latch 38 disposedin cascade between an input terminal and an output terminal. Each stageof the shift register 22 outputs a start pulse or an output pulse (in)of a previous stage by delaying it for as much as one clock period inresponse to first and second clock signals (cka, ckb) which haveopposite phases, and generates the output pulse (in) which overlaps theoutput pulse (in) of the previous stage by as much as one clock period.

The first clock signal (ckb) is inputted to a non-inversion controlterminal of the first inverter type tri-state buffer 31 and the secondclock signal (cka) is inputted to an inversion control terminal of thefirst inverter type tri-state buffer 31. The start pulse or the outputpulse (in) of the previous stage is inputted to the input terminal. Thefirst inverter type tri-state buffer 31 inverts the output pulse (in) ofthe previous stage or the start pulse to supply to the first latch 37when the first clock signal (cka) of logic high is supplied to thenon-inversion control terminal and the second clock signal (ckb) oflogic low is supplied to the inversion control terminal. The firstinverter type tri-state buffer 31 is changed to a high impedance stateso as not to transmit the start pulse of the output pulse (in) of theprevious stage to the first latch 37 when the first clock signal (cka) alogic low level is supplied to the non-inversion control terminal or thesecond clock signal (ckb) of logic high level is supplied to theinversion control terminal.

The first latch 37 includes a first inverter 32 and a third invertertype tri-state buffer 33 which are connected within a closed loopbetween the first inverter type tri-state buffer 31 and the secondinverter type tri-state buffer 34. The first latch 37 latches the outputof logic high, inverts the output and supplies the inverted output tothe second inverter type tri-state buffer 34 when the output of thefirst inverter type tri-state buffer 31 is at logic high.

The second inverter type tri-state buffer 34 inverts the output from thefirst latch 37 to supply to the second latch when the second clocksignal (ckb) of a logic high level is supplied to the non-inversioncontrol terminal and the first clock signal (cka) of logic low level issupplied to the inversion control terminal at the same time.

The second latch 38 includes a second inverter 35 and a fourth invertertype tri-state buffer 36 which are connected within a closed loopbetween the second inverter type tri-state buffer 34 and an outputterminal. The second latch 38 latches the output of logic high, invertsthe output, and supplies the inverted output to the output terminal andsimultaneously generates a start pulse (In+1) for the next shiftregister stage when the output of the second inverter type tri-statebuffer 34 is at a logic high level.

As shown in FIG. 4, the outputs S1 to S42 of the stages are shiftedwhile being overlapped by as much as one clock period. The outputs S1 toS42 sequentially turn on the switch devices 24A that are included in thechannel selecting part 24 shown in FIG. 2.

The shift register configured with the stages as illustrated in FIG. 3has an advantage that the operating speed of the channel selecting part24 can be increased by the amount of the overlapping period between theshifted outputs. On the other hand, such a shift register has a problemthat a capacitance between the gate terminal and the source/drain isrelatively high because a clock signal line is connected to the gateterminal of an MOS TFT used for each of the inverter type tri-statebuffers. The high capacitance generates signal delays that limit theusable frequency of the clock signal. Further, the high capacitancecauses increased power consumption if the drive voltage is increased tooperate at high speeds.

FIG. 5 illustrates one stage a shift register 22 having a configurationin which the output pulses are not overlapped.

Referring to FIG. 5, an arbitrary stage of the shift register 22includes a first multiplexer 51, an OR circuit 52, a second multiplexer53, and first to fifth inverters 54 to 58.

Each of the multiplexers 51 and 53 has a circuit configuration in whichtwo transmission gates are symmetrically connected, and the multiplexeroutputs an input signal applied to a first input terminal (in1) when alogic high signal is supplied to a non-inversion control terminal butoutputs an input signal applied to a second input terminal (in2) when alogic high signal is supplied to an inversion control terminal.

The OR circuit 52 includes an NOR gate having two input terminals and aninverter. The output of the first inverter 54 is supplied to the secondinput terminal of the NOR gate as feedback and the output of the firstmultiplexer 51 is supplied to the first input terminal of the NOR gate.The OR circuit inverter inverts the output of the NOR gate. The ORcircuit 52 generates an output which is a logical sum (OR) of the twoinput terminals to the NOR gate.

The shift register 22, using the shift register stages illustrated inFIG. 5, has an advantage that the capacitance load is low because theclock signal line is connected to the source/drain terminal of the MOSTFT which constitutes the transmission gate and because most of the MOSTFTs are in an off state during operation. However, a shift register 22employing register stages as illustrated in FIG. 5 has the problem thatoutputs cannot be overlapped.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a shift register and aliquid crystal display device using the same that substantially obviatesone or more of the problems due to limitations and disadvantages of therelated art.

An advantage of the present invention is to provide a shift registerhaving a low capacitance loading and allowing output overlapping, and aliquid crystal display device using the same.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention. Theobjectives and other advantages of the invention will be realized andattained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described, a shiftregister having a plurality of stages is provided wherein each of thestages includes: an input circuit part arranged to receive an inputsignal; an exclusive OR circuit arranged to generate a toggle signal byan exclusive OR operation on a non-inversion output and an inversionoutput of the input circuit part; and an output circuit part arranged tosupply one of a clock signal and a feedback signal from an outputterminal to the output terminal and an input terminal of the next stagein response to the toggle signal, wherein each of the stages is arrangedto generate output signals partially overlapped with output signals fromother stages and of which the phases are sequentially shifted.

In another aspect of the present invention, liquid crystal displaydevice, includes: a liquid crystal display panel having a plurality ofdata lines, a plurality of gate lines crossing the plurality of datalines, and a plurality of liquid crystal cells; a data driver to convertdigital data into analog data; a channel selecting part arranged tosequentially select analog outputs of the data driver; a sampling andholding part arranged to sample the analog data from the channelselecting part to supply the sampled data to the data lines; and a gatedriver-to sequentially supply gate pulses to the gate lines, wherein atleast one of the data driver, the channel selecting part and the gatedriver includes a shift register having a plurality of stages, eachstage an input circuit part arranged to receive an input signal; anexclusive OR circuit arranged to generate a toggle signal by anexclusive OR operation on a non-inversion output and an inversion outputof the input circuit part; and an output circuit part arranged to supplyone of a clock signal and a feedback signal from an output terminal tothe output terminal and an input terminal of the next stage in responseto the toggle signal, wherein each of the stages is arranged to generateoutput signals partially overlapped with output signals from otherstages and of which the phases are sequentially shifted.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention.

In the drawings:

FIG. 1 is a black diagram briefly illustrating a liquid crystal displaydevice;

FIG. 2 is a block diagram illustrating an analog sampling & holdingcircuit;

FIG. 3 is a circuit diagram of a shift register supporting outputoverlapping;

FIG. 4 is an input/output waveform diagram of a stage illustrated inFIG. 3;

FIG. 5 is a circuit diagram illustrating an OR type stage for the shiftregister;

FIG. 6 is a block diagram illustrating a liquid crystal display deviceaccording to an embodiment of the present invention;

FIG. 7 is a block diagram illustrating a data driver shown in FIG. 6;

FIG. 8 is a circuit diagram illustrating a stage of a shift registershown in FIG. 6; and

FIG. 9 is an input/output waveform diagram of the stage shown in FIG. 8.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to an embodiment of the presentinvention, example of which is illustrated in the accompanying drawings.

Embodiments of the present invention will be explained hereinafter withreference to FIG. 6 to 9.

Referring to FIG. 6, a liquid crystal display device according to anembodiment of the present invention includes a liquid crystal displaypanel 62 having data lines DL1 to DLm which cross gate lines GLl to GLnand TFTs for driving liquid crystal cells Clc formed at crossings of thedata and gate lines; a data driver 63 for converting digital data RGBinto an analog data voltage; a channel selecting part 64 and a sampling& holding part 65 disposed between the data driver 63 and the data linesDL1 to DLm of the liquid crystal display panel 62; a gate driver 69 forsupplying a gate pulse to the gate lines GL1 to GLn of the liquidcrystal display panel 62; a gamma reference voltage generator 66 forsupplying a gamma reference voltage to the data driver 63; a timingcontroller 61 for controlling the data driver 63 and the gate driver 69;and a shift register 67 for controlling a sequential operation of thechannel selecting part 64.

The liquid crystal display panel 62 includes a layer of liquid crystalbetween two glass substrates. The data lines DL1 to DLm and the gatelines GL1 to GLn cross each other on a lower of the two glass substratesof the liquid crystal display panel 62. A TFT is formed near thecrossing of the data lines DL1 to DLm and the gate lines GLl to GLn. TheTFT supplies the data of the data lines DLl to DLm to liquid crystalcells Clc in response to a gate pulse. To this end, a gate electrode ofthe TFT is connected to the gate line GL1 to GLm, a source electrode ofthe TFT is connected to the data line DL1 to DLm. A drain electrode ofthe TFT is connected to a pixel electrode in each liquid crystal cellClc. Further, storage capacitors for maintaining the voltage of theliquid crystal cells are formed on the lower glass substrate of theliquid crystal display panel 62.

The timing controller 61 samples the digital video data supplied from adigital video card of a system (not shown) to supply to the data driver63. Further, the timing controller 61 generates a data control signalDDC and a gate control signal GDC by use of horizontal and verticalsynchronization signals H and V which are supplied to the timingcontroller 61. The data control signal DDC includes a source shift clockSSC, a source start pulse SSP, a polarity control signal POL, a sourceoutput enable signal SOE, etc, and is supplied to the data driver 63.The gate control signal GDC includes a gate start pulse GSP, a gateshift clock GSC, a gate output enable GOE, etc, and is supplied to thegate driver 69.

The gate driver 69 sequentially generates a scan pulse, i.e., a gatehigh pulse, in response to a gate drive control signal GDC supplied fromthe timing controller 61. The gate driver 69 includes a shift registerthat sequentially generates the scan pulse, and a level shifter thatshifts a swing width of the voltage of the scan pulse to a rangesuitable for driving the liquid crystal cell Clc. The TFT is turned onin response to the scan pulse from the gate driver 69. When the TFT isturned on, the video data on the data line DLl to DLm are supplied tothe pixel electrode of the liquid crystal cell.

The gamma reference voltage generator 66 supplies a designated number ofpositive gamma reference voltages GH and a designated number of negativegamma reference voltages GL to the data driver 63. The positive gammareference voltage GH and the negative gamma reference voltage GL aregenerated by use of voltage division resistances.

The data driver 63 supplies the data to the data lines DLl to DLm inresponse to the data control signal DDC supplied from the timingcontroller 61. The data driver 63 samples the digital data RGB from thetiming controller 61, latches the data, and then converts the data intothe analog gamma voltage. The data driver 63 includes a plurality ofdata integrated circuits having a configuration as in FIG. 7.

The shift register 67 generates output signals that are overlapped andshifted, as a switch control signal of the channel selecting part 64 inresponse to the source start pulse SSP and any one of the clock signalsHCK1 to HCK4.

The channel selecting part 64 may be realized using CMOS TFTs connectedto the output terminal of the data driver 63 in a one-to-onerelationship. The channel selecting part 64 includes a plurality ofswitch devices that supply the output of the data driver 63 to thesampling & holding part 65 in response to each of the overlapping andshifted output signals of the shift register 67.

The sampling & holding part 65 simultaneously supplies the analogvoltages to the data lines DL1 to DLm after sampling and holding theanalog data voltages from the channel selecting part 64.

FIG. 7 is illustrates a data integrated circuit configuration of thedata driver.

Referring to FIG. 7, the data integrated circuit includes a dataregister 71 to which the data RGB is inputted from the timing controller61; a shift register 72 for generating a sampling clock; a latch 73connected between the shift register 72 and k (where, k is an integerless than m, the number of data lines of the liquid crystal displaypanel) number of data lines DL1 to DLk; a digital to analog converter(hereinafter, referred to as ‘DAC’) 74; an output buffer 75; and a gammavoltage supplier 76 connected between the gamma reference voltagegenerator 66 and the DAC 74.

The shift register 72 shifts the source start pulse SSP from the timingcontroller 61 to generate a sampling signal in accordance with thesource sampling signal SSC. Further, the shift register 72 shifts thesource start pulse SSP to transmit a carry signal CAR to the shiftregister 72 of a next data integrated circuit.

The latch 73 sequentially samples the data RGB from the data register 71to latch line by line in response to the sampling signal sequentiallyinputted from the shift register 72, and then simultaneously outputs thesampled data in response to the source output enable signal SOE.

The DAC 74 converts the data from the latch 73 into an analog gammavoltage DGH, DGL from the gamma voltage supplier 76. The gamma voltageDGH, DGL is an analog voltage corresponding to a graylevel of thedigital input data.

The gamma voltage supplier 76 subdivides the gamma reference voltageinputted from the gamma reference voltage generator 66 to supply thegamma voltage corresponding to the gray level to the DAC 74. The gammavoltage supplier 76 comprises a circuit for generating a positive gammavoltage and a circuit for generating a negative gamma voltage.

The embodiment of the present invention as described with reference toFIG. 6 and 7 sequentially samples a fixed number of digital data andgenerates the analog signal by transmitting the data latched at thelatch 73 to the DAC 74, as compared to the data driver of the relatedart which includes a first latch for sampling the data linesequentially; a second latch for latching the data from the first latchwhile the voltage is converted by the DAC. For example, if the designednumber of data lines is 240 (as in a QVGA display) and the number oflatches 73 and DACs 74 is 40 , a converting time of the DAC 74 and acharging time of the data line is about e,fra 1/6 of one horizontal time1H (=40/240). The output of the DAC 74 is transmitted to a 40 ^(th) dataline by each of the channel selecting part 64 and the sampling & holdingpart 65 which are sequentially opened for about H/6 period. For example,the first DAC 74 sequentially charges and maintains 40n+1 (where n=0, 1,2, 3, 4, and 5) data lines with an interval of H/6 time period. Thechannel selecting part 64 is configured similarly to a one bank analogdriving method of the related art, as shown in FIG. 2, and thus abrightness non-uniformity phenomenon associated with a bank boundarygenerated when a plurality of banks are used does not occur. The numberof the latches 73 and DACs 74 are reduced to ⅙ in comparison with thedata driver of the digital driving method of the related art, thusallowing the circuitry to be embedded in a relatively small area.Further, the external digital data signal RGB may be applied directly tothe data driver 63 without passing through the timing controller 61,allowing further simplification of the timing controller 61 circuitry.

FIG. 8 illustrates the configuration of a stage of the shift register 67shown in FIG. 6. FIG. 9 illustrates input/output waveforms of the stageshown in FIG. 8. A detail configuration and operation of a shiftregister stage will be explained assuming that the stage is a firststage of the shift register 67.

Referring to FIG. 8, a first stage of the shift register 67 includes afirst multiplexer 81, a first inverter 82, an exclusive OR circuit 83, asecond inverter 84, a second multiplexer 85 and third to sixth inverters86 to 89 that are disposed in cascade between an input terminal and anoutput terminal.

Each of the multiplexers 81 and 85 has a circuit configuration in whichtwo transmission gates are symmetrically connected, and the multiplexeroutputs an input signal of a first input terminal (in1) when a logichigh signal is supplied to a non-inversion control terminal and outputsan input signal of a second input terminal (in2) when a logic highsignal is supplied to an inversion control terminal.

The source start pulse SSP is inputted to the first and second inputterminals (in1, in2) of the first multiplexer 81, and a control signalis inputted to the non-inversion control terminal and inversion controlterminal of the first multiplexer 81.

The first inverter 82 is connected between an output node of the firstmultiplexer 81 and the input terminal of one side of the exclusive ORcircuit 83 and inverts the output of the first multiplexer 81 to supplyto the input terminal of one side of the exclusive OR circuit 83.

The exclusive OR circuit 83 outputs a toggle signal (ql) by performingan XOR operation on the output of the first multiplexer 81 and theoutput of the first inverter 82. To this end, the exclusive OR circuit83 includes three NAND gates 90, 91, and 92. The first NAND gate 90performs a NAND operation on feedback input from the third inverter 86and the output of the first multiplexer 81 to supply a signal to asecond input terminal of the third NAND gate 92, and the second NANDgate 91 performs a NAND operation on the output of the first inverter 82and a feedback input from the fourth inverter 87 to supply to a firstinput terminal of the third NAND gate 92. The third NAND gate 92performs a NAND operation on the outputs from the first NAND gate 90 andthe second NAND gate 91.

The second inverter 84 is connected between the exclusive OR circuit 83and the second multiplexer 85 to invert the output of the exclusive ORcircuit 83 to supply to the inversion control terminal of the secondmultiplexer 85.

The second multiplexer 85 outputs a clock signal HCK1 when the togglesignal (q1) inputted to the non-inversion control terminal is a logichigh, and outputs the feedback from the fourth inverter 87 when theoutput of the second inverter 84 inputted to the inversion controlterminal is a logic high signal.

The third inverter 86 inverts the output of the second multiplexer 85and inputs to the second input terminal of the first NAND gate 90 of theexclusive OR circuit 83 to toggle the toggle signal (q1). The fourthinverter 87 inverts the output of the third inverter 86 and inputs tothe second input terminal (in2) of the second multiplexer 85 and thesecond input terminal of the second NAND gate 91 to toggle the togglesignal (q1).

The output of the fourth inverter 87 is supplied to a start pulse inputterminal of the next stage as a start pulse of the next stage.

The fifth inverter 88 inverts the output of the third inverter 86 andthe inverted signal is output as a control signal of a pMOS FET thatconstitutes a part of the CMOS of the channel selecting part 64.

The sixth inverter 89 inverts the output of the fourth inverter 87 andthe inverted signal is output as a control signal of an nMOS FET thatconstitutes part of the CMOS of the channel selecting part 64.

The output of the stage generates overlapped output signals SI to S8,wherein the output signals are shifted as much as the toggle signals(q1-q8) are overlapped in adjacent stages, as shown in FIG. 9. Theoutput signals Sl to S8 sequentially turn on the switch devices of thechannel selecting part 64.

In the shift register stage described above, the first toggle signal(q1) is generated at a rising time of the source start pulse SSP togenerate the output as a logic high, while the second toggle signal (q2)is generated at a falling time of the source start pulse SSP to invertthe output to a logic low. The stage of FIG. 8 has a very lowcapacitance loading because the clock signal line is connected to thesource/drain terminal of the TFT, which constitutes the secondmultiplexer 85 and the second multiplexer 85 remains in an off stateexcluding one or two stages in which the toggle signal is generated.

The shift register according to the present invention can be applied asthe shift register of the data driver 63 and/or the gate driver 69, aswell as the shift register for controlling the channel selecting part.

As described above, the shift register and the liquid crystal displaydevice using the same according to the present invention have a lowcapacitance load and overlapping outputs, thereby enabling improved(higher) the driving speeds.

It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. A liquid crystal display device, comprising: a liquid crystal displaypanel having a plurality of data lines, a plurality of gate linescrossing the plurality of data lines, and a plurality of liquid crystalcells; a data driver to convert digital data into analog data; a channelselecting part arranged to sequentially select analog outputs of thedata driver; a sampling and holding part arranged to sample the analogdata from the channel selecting part to supply the sampled data to thedata lines; and a gate driver to sequentially supply gate pulses to thegate lines, wherein at least one of the data driver, the channelselecting part and the gate driver includes a shift register having aplurality of stages, each stage includes an input circuit part arrangedto receive an input signal; an exclusive OR circuit arranged to generatea toggle signal by an exclusive OR operation on a non-inversion outputand an inversion output of the input circuit part; and an output circuitpart arranged to supply one of a clock signal and a feedback signal froman output terminal to the output terminal and an input terminal of thenext stage in response to the toggle signal, wherein each of the stagesis arranged to generate output signals partially overlapped with outputsignals from other stages and of which the phases are sequentiallyshifted.
 2. The liquid crystal display device according to claim 1,wherein the input circuit part includes: a first multiplexer arranged toreceive the input signal; and a first inverter arranged to invert anoutput signal from the first multiplexer.
 3. The liquid crystal displaydevice according to claim 2, wherein the exclusive OR circuit includes:a first NAND gate arranged to generate an output by a NAND operation onan output signal of the first multiplexer and the feedback signal; asecond NAND gate arranged to generate an output by a NAND operation onan output signal from the first inverter and the feedback signal; and athird NAND gate arranged to generate an output by a NAND operation onoutput signals from the first and second NAND gates.
 4. The liquidcrystal display device according to claim 3, wherein the output circuitpart includes: a second inverter arranged to invert an output from thethird NAND gate; a second multiplexer arranged to output one of theclock signal and the feedback signal in response to the output from thethird NAND gate and an output signal from the second inverter; a thirdinverter arranged to invert an output from the second multiplexer togenerate the feedback signal; and an output terminal inverter circuitarranged to invert the feedback signal to generate an inversion outputand a non-inversion output.
 5. The liquid crystal display deviceaccording to claim 4, wherein the output terminal inverter circuitincludes: a third inverter arranged to invert an output signal from thesecond multiplexer and to input the inverted signal output signal fromthe second multiplexer to a first NAND gate of the exclusive OR circuitto toggle a toggle signal (q1); a fourth inverter arranged to invert anoutput signal from the third inverter and to input the signal invertedby the fourth inverter to the second multiplexer and a second NAND gatearranged to toggle the toggle signal (q1); a fifth inverter arranged toinvert the output signal from the third inverter and to output thesignal inverted by the fifth inverter as a control signal; and a sixthinverter arranged to invert an output signal from the fourth inverterand to output the signal inverted by the sixth inverter as the controlsignal.
 6. The liquid crystal display device according to claim 5,wherein the signal inverted by the fifth inverter is to control as acontrol signal of pMOS FET constituting a CMOS of the channel selectingpart.
 7. The liquid crystal display device according to claim 5, whereinthe signal inverted by the sixth inverter is to control a control signalof nMOS FET constituting a CMOS of the channel selecting part.
 8. Theliquid crystal display device according to claim 5, wherein the outputof the fourth inverter is to supply a start pulse of another stage.
 9. Ashift register for driving a liquid crystal display device having aplurality of stages, wherein each of the stages includes: an inputcircuit part arranged to receive an input signal; an exclusive ORcircuit arranged to generate a toggle signal by an exclusive ORoperation on a non-inversion output and an inversion output of the inputcircuit part; and an output circuit part arranged to supply one of aclock signal and a feedback signal from an output terminal to the outputterminal and an input terminal of the next stage in response to thetoggle signal, wherein each of the stages is arranged to generate outputsignals partially overlapped with output signals from other stages andof which the phases are sequentially shifted.
 10. The shift registeraccording to claim 9, wherein the input circuit part includes: a firstmultiplexer arranged to receive the input signal; and a first inverterarranged to invert an output signal from the first multiplexer.
 11. Theshift register according to claim 10, wherein the exclusive OR circuitincludes: a first NAND gate arranged to generate an output by a NANDoperation on an output signal of the first multiplexer and the feedbacksignal; a second NAND gate arranged to generate an output by a NANDoperation on an output signal from the first inverter and the feedbacksignal; and a third NAND gate arranged to generate an output by a NANDoperation on output signals from the first and second NAND gates. 12.The shift register according to claim 11, wherein the output circuitpart includes: a second inverter arranged to invert an output from thethird NAND gate; a second multiplexer arranged to output one of theclock signal and the feedback signal in response to the output from thethird NAND gate and an output signal from the second inverter; a thirdinverter arranged to invert an output from the second multiplexer togenerate the feedback signal; and an output terminal inverter circuitarranged to invert the feedback signal to generate an inversion outputand a non-inversion output.
 13. The shift register according to claim12, wherein the output terminal inverter circuit includes: a thirdinverter arranged to invert an output signal from the second multiplexerand to input the inverted signal output signal from the secondmultiplexer to a first NAND gate of the exclusive OR circuit to toggle atoggle signal (q1); a fourth inverter arranged to invert an outputsignal from the third inverter and to input the signal inverted by thefourth inverter to the second multiplexer and a second NAND gatearranged to toggle the toggle signal (q1); a fifth inverter arranged toinvert the output signal from the third inverter and to output thesignal inverted by the fifth inverter as a control signal; and a sixthinverter arranged to invert an output signal from the fourth inverterand to output the signal inverted by the sixth inverter as the controlsignal.
 14. The shift register according to claim 13, wherein an outputsignal from the fourth inverter is supplied as a start pulse of anotherstage.
 15. A method for driving a liquid crystal display comprising:providing a shift register having a sequence of stages; receiving aninput signal in an input circuit of a first stage of the sequence ofstages; generating a toggle signal using an exclusive OR operation on anon-inversion output and an inversion output of the input circuit of thefirst stage; supplying one of a clock signal and a feedback signal froman output terminal of the first stage to the output terminal and aninput terminal of the next stage in response to the toggle signal; andgenerating an output signal from the first stage partially overlappedwith an output signal generated from a next stage of the sequence ofstages, wherein output signals from the sequence of stages aresequentially shifted.